1. Field of the Invention
This invention relates generally to bridge devices, and more particularly to bridge devices that prefetch data from devices on one bus for transfer to devices on another bus.
2. Description of the Related Art
Modem computer systems typically employ buses to convey information between various parts in the computer systems. For example, computer systems generally include one or more buses to connect a central processing unit (CPU) to a main memory and input/output (I/O) devices for transferring data and control signals. Today, one of the most widely used buses is peripheral component interface (PCI) bus.
With the proliferation of I/O devices such as disk drives, tape drives, printers, scanners, audio/video devices, etc., the PCI bus is used to connect an increasing number of I/O devices. To accommodate the addition of more I/O devices, conventional computer systems typically provide one or more secondary PCI buses in addition to a primary PCI bus. For example, FIG. 1 illustrates a schematic block diagram of a conventional computer system 100 that includes a primary host PCI bus 104 and a secondary PCI bus 112. In the computer system 100, the primary PCI bus 104 is coupled to a host bus bridge 108 on the host side and a PCI-to-PCI bridge 106 on the other. A CPU 102 and a main memory I 10 are coupled to the host bus bridge 108. The host bus bridge 108 provides host chipset and functions as a memory controller in accessing the main memory 110. In this configuration, the CPU 102 accesses the main memory 110 through the host bus bridge 108 to read or store information. The primary PCI bus 104 may also be coupled to other devices such as hard disk drives, audio/video devices, etc.
The secondary PCI bus 112 is coupled to the PCI-to-PCI bridge 106, a pair of SCSI adapters, and a local CPU 116. The SCSI adapter 114 is connected to a plurality of SCSI drives 126 and 128 to provide additional storage capacity to the computer system 100. On the other hand, the SCSI adapter 118 is coupled to a SCSI drive 120, a tape drive 122, and a CD drive 124 to enhance capabilities of the computer system 100. Similarly, the local CPU 116 provides additional processing capabilities and may be used, for example, as an I/O controller, audio/video processor, etc.
The PCI-to-PCI bridge 106 is coupled between the primary PCI bus and a secondary PCI bus 112 and functions to facilitate communication between the PCI devices coupled to the primary PCI bus 104 and the secondary PCI bus 112. The PCI devices are often called PCI agents, which include both PCI master and slave devices. The PCI-to-PCI bridge 106 may include an arbiter (not shown) for arbitrating access to the secondary PCI bus 112 among the PCI agents such as PCI devices 114, 116, and 118.
The PCI-to-PCI bridge 106 allows mapping of address space of one bus into the address space of the other bus through the use of internal configuration registers. Conventional PCI bridges are well known and is described, for example, in U.S. Pat. No. 5,918,026, entitled xe2x80x9cPCI to PCI Bridge for Transparently Completing Transactions between Agents on Opposite Sides of the Bridge,xe2x80x9d and in U.S. Pat. No. 5,905,877 entitled xe2x80x9cPCI Host Bridge Multi-Priority Fairness Arbiter.xe2x80x9d In addition, details of PCI specification and bus systems are amply described by Tom Shanley et al. in PCI System Architecture (3rd ed. 1995). The disclosures of these references are incorporated herein by reference.
Conventional PCI-to-PCI bridges may be implemented in a variety of ways. For example, they may be implemented with or without a prefetch buffer for buffering data received from one bus for transfer to another bus. In performing a data transfer, however, a PCI-to-PCI bridge without a prefetch buffer may require substantial arbitration and command overhead. For instance, in response to a read command from a master, the bridge performs xe2x80x9csingle-cyclexe2x80x9d reads on the target bus and then return the data from that cycle to the original master. If the master still wants more data, a new read command is issued on the target bus. This process is repeated until the original master has received all of the data it requires. Thus, for masters that require a significant amount of data, such bridge is generally not desirable since most of the bus bandwidth is wasted on arbitration and command overhead.
On the other hand, PCI bridges having prefetch buffers generally provide an improved performance. These buffers, often called xe2x80x9cprefetch buffers,xe2x80x9d are used to store data fetched from one PCI device over one PCI bus to another PCI device connected to another PCI bus. One approach has implemented the prefetch buffer as a single buffer that is shared for bursts in both bus directions across the bridge. This allows only a single transaction across the bridge to be active at any given time. In another approach, multiple prefetch buffers are provided so that more than one transaction can be active simultaneously. The multiple buffers reduce the number of separate bursts that needs to be performed, thereby improving performance.
By way of example, the SCSI adapter 114 arbitrates for the secondary PCI bus and requests, as a bus master (i.e., initiator), data from the main memory 110 by issuing a read request to the PCI-to-PCI bridge 106. The bridge 106 queues the read request and issues a proxy read request to the host bus bridge 108. In addition, the bridge 106 issues a retry request to the bus master so that the SCSI adapter 114 periodically reissues the read request until it receives the requested data from the bridge 106. The host bus bridge 108 communicates with the main memory 110 to transfer the requested data from the main memory 110 to the bridge 106. The PCI-to-PCI bridge 106 receives the data from the host bus bridge 108 and stores in its prefetch buffer for transfer to the SCSI adapter 114.
Unfortunately, the amount of data that is prefetched on the target bus often does not match the amount of data required by the original master (e.g., SCSI adapter 114). This is because the amount of data to be prefetched is typically programmed in the bridge 106 to a single fixed size for all masters connected to the secondary PCI bus 112. However, the data requirement of one PCI device may be quite different from another PCI device. For example, one PCI master device may need only 32 bits of data per read operation while another master device may need 4 Kbytes of data. Hence, a single, fixed prefetch size may be too small for some masters and too large for others, thereby wasting bus bandwidth in either case.
Given the fixed prefetch size, conventional bridges were generally optimized for either small bursts or large bursts of data transfer. In this scenario, a bridge that was optimized for small bursts might prefetch only a single 32 -bit word for each read. If the master device required a much larger data, the read operation would have to be broken up into many single word read commands on each PCI bus. As can be appreciated, this would be highly inefficient approach compared to completing the data transfer-in a single burst. At the other extreme, a bridge that has been optimized for large bursts may prefetch 128 bytes or more. On a 32 -bit PCI bus, a 128 byte prefetch would consume 32 data cycles. For a master that requires only a single word of read data, for example, 31 of these cycles would be wasted.
Furthermore, a PCI bus may currently accommodate up to 10 PCI devices. Since a PCI bridge is treated as a PCI device, this means that up to 9 PCI master devices with differing data transfer requirements may be attached to the PCI bus. As more master devices are attached to the secondary PCI bus 112 with differing data needs, the problem of prefetch data size mismatch with attendant loss in performance is exacerbated.
Thus, what is needed is a PCI bridge and method for transferring data between two PCI buses in sizes that are specific to each of the master devices so as to improve data transfer performance.
The present invention fills these needs by providing bridge device for transferring data using master-specific prefetch sizes. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, a method, or a computer readable medium. Several inventive embodiments of the present invention are described below.
In one aspect of the invention, the present invention provides a bridge device for transferring data between master and slave devices. The bridge device is coupled between a first bus and a second bus with the master devices being coupled to the first bus and the slave devices being coupled to the second bus. The bridge device includes a set of prefetch control registers, a prefetch buffer, and bridge control circuitry. The set of prefetch control registers is arranged to store prefetch sizes of data to be prefetched for a set of the master devices with one prefetch control register being provided for a master device. The prefetch buffer is arranged to store data for transfer. The bridge control circuitry is coupled to the prefetch control registers and the prefetch buffer for transferring data between a source device and a destination device. The bridge control circuitry is further arranged to receive a first data transfer request from a selected master device for transferring data between the selected master device and a selected slave device. The bridge control circuitry issues a second data transfer request to the selected slave device for transferring the data. The bridge control circuitry receives the requested data from the source device and stores the received data in the prefetch buffer. The bridge control circuitry transfers the stored data from the prefetch buffer to the destination device when the prefetch buffer receives and stores data size that correspond to the prefetch size stored in a prefetch control register associated with the selected master device.
In another aspect of the invention, the present invention provides a bridge device for transferring data between first devices and second devices with the bridge being coupled between a first bus and a second bus. The first devices are coupled to the first bus and the second devices are coupled to the second bus. The bridge device includes a set of prefetch control registers, a prefetch buffer, an arbiter, and bridge control circuitry. The set of prefetch control registers is arranged to store prefetch sizes of data to be prefetched for a set of the first devices with one prefetch control register for one first device. The prefetch buffer is arranged to receive and store data from a source device for transfer to a destination device. The arbiter is arranged to receive requests by one or more first devices for access to the first bus and grants a selected first device access to the first bus. The bridge control circuitry is coupled to the prefetch control registers and the prefetch buffer for transferring the data. The bridge control circuitry is also arranged to receive a first data transfer request from the selected first device for transferring data to or from a selected second device such that one device is the source device and the other device is the destination device. The bridge control circuitry issues a second data transfer request to the selected second device for transferring the data, wherein the bridge control circuitry receives the requested data from the source device and stores the received data in the prefetch buffer. The bridge control circuitry transfers the stored data from the prefetch buffer to the destination device when the prefetch buffer contains data matching the prefetch size in a prefetch control register associated with the selected first device.
In yet another aspect of the invention, a method is disclosed for transferring data between first devices and second devices. The first devices are coupled to the first bus and the second devices are coupled to the second bus. The method includes (a) storing prefetch sizes of data to be prefetched for a plurality of first devices in a plurality of prefetch control registers, one prefetch control register for each first device; (b) arbitrating for the first bus by one or more first devices and granting access to a selected first device as a bus master; (c) receiving a first data transfer request from the selected first device for transferring data to or from a selected second device such that one device provides the data as a source device and the other device receives the data as a destination device; (d) issuing a second data transfer request to the selected second device over the second bus; (e) receiving the requested data from the source device and storing the received data in a prefetch buffer; and (f) when the prefetch buffer contains the data of the prefetch size associated with the selected first device, transferring the stored data from the prefetch buffer to the destination device.
Preferably, the first and second buses are PCI buses. In one embodiment, the prefetch control registers store a set of prefetch parameters for different types of read commands. In addition, the buffer may be segmented into a plurality of segments so that data transfer requests from a plurality of master devices may be carried out by assigning a buffer segment to one of the plurality of master devices.